This invention relates generally to the testing of analog or mixed-signal integrated circuits and, in particular, to a test bus circuit suitable for testing multiple high-speed analog circuits disposed on a common substrate.
The observation and control of signals in integrated circuits is necessary for the manufacturing testing and diagnosis of the integrated circuits. However, modern digital, analog and mixed-signal integrated circuits, which comprise of hundreds of thousands or even millions of interconnected circuit elements disposed on a common semiconductor substrate, are often difficult to test because the signals inside the integrated circuits are not directly observable and controllable. For digital circuits, many techniques have been developed that address this problem including scan-path design and the IEEE 1149.1 (commonly known as JTAG) standard. These techniques typically employ scan registers or other dedicated logic such that the storage elements in a digital circuit can be used as direct observation and control points, independent of their proximity to the functional interface of the circuit.
Digital circuits benefit from the fact that digital signals can be observed, controlled and brought in proximity to each other through multiplexing or other combinatorial operations with little or no effect on their normal intended function. This is because coupling mechanisms (principally capacitive and conductive) that are common to all proximate signals on a chip are of such a magnitude that they have little deleterious effect on digital signals. As a result, digital circuits can be accurately tested using these techniques without affecting the normal operation of the circuit in any appreciable way.
For analog or mixed-signal integrated circuits, there is also a strong need to observe and control signals for testing and diagnosis. Since the analog signals generated by these integrated circuits include both voltage and frequency (or time-dependent) information, however, it is necessary to stimulate or analyze the complete full-bandwidth properties of the signals. A parametric analysis of the properties and integrity of the analog signals is often critical to understanding the functioning of the analog or mixed-signal integrated circuit. This is very different from digital signal analysis, which usually consists of a simple static analysis of logical signal values.
Analog signals, especially in communications and other high-speed applications, do not have the same immunity from degradation as digital signals because they are typically subject to very stringent signal integrity requirements. Consequently, analog signals are often specially routed and shielded in circuit design and construction to avoid coupling mechanisms to other nearby analog or digital circuits or signals, or to signals of such a nature as to cause destructive interference regardless of their proximity.
For the above-mentioned reasons, conventional scan techniques that are used to test digital circuits cannot be used to test analog or mixed-signal integrated circuits. For example, if simple multiplexing transistors and scan circuits are used to transmit multiple analog signals between external observation or control points and analog circuits under test, an unacceptable level of degradation in one or more critical signal properties would typically occur. The signal degradation is primarily caused by the capacitive coupling between the multiplexing transistors and between the analog signals that are brought to the multiplexing point. In earlier integrated circuit designs, such degradation was often acceptable. However, with the recent advent of integrated circuits capable of very-high rate analog signal processing, made possible by the development of deep sub-micron circuit technologies, this level of degradation cannot be tolerated.
Conventional scan techniques are unsuitable for testing analog or mixed-signal integrated circuits also because they require signals to be stored for observation or read-out at a later time. However, analog signals are usually not static, so they cannot be readily or inexpensively stored. Furthermore, the storage of a signal implies that a non-real-time analysis of the properties or logical functioning of the signal is useful. Since most important properties of analog signals in modern analog or mixed-signal integrated circuits must be observed in real-time, however, conventional scan techniques cannot be used.
To preserve their integrity, analog signals may be observed or controlled directly through the pins of the integrated circuit package. To implement directly observable and controllable points in an integrated circuit, it is generally required that multiple test pins be added to the package of the integrated circuit. However, the additional pins significantly increase the cost of the integrated circuit because the cost of the integrated circuit package, which is typically greater than the cost of the silicon chip itself, is principally determined by the pin count.
The integrity of analog signals can also be preserved by placing a shield around the conductors on the integrated circuit. A shield electrically isolates a signal transmitted on a conductor from interfering electric fields. Shields are commonly used in the manufacture of non-integrated electronics and coaxial cables. Shielding signals on modern integrated circuits, however, is problematic because the shield must be placed very close to the conductor being shielded and thus often presents an unacceptably large capacitive load on the conductor.
The useful observation and control of analog signals for the purpose of manufacturing testing and diagnosis sometimes requires that other analog circuits on the integrated circuit function during testing. As mentioned earlier, however, conventional scan techniques typically suffer from crosstalk such that the testing of an analog circuit may interfere with the normal operation of nearby or related circuits.
The above-described limitations on the observation and control of analog signals exist in stark contrast to the scan methodology used in the digital world, where a circuit often can be transformed from a functional mode to a test mode at will to facilitate the use of the scan path registers.
In view of the shortcomings of the earlier approaches to testing analog or mixed-signal integrated circuits, it is an object of the present invention to maintain a high level of signal integrity and observation or stimulation bandwidth when observing or controlling signals in analog or mixed-signal integrated circuits.
Another object of the invention is to observe or control signals in analog or mixed-signal integrated circuits without interfering with the normal operation of nearby or related circuits.
A further object of the invention is to minimize the number of pins necessary to observe or control signals in analog or mixed-signal integrated circuits.
The present invention consists of an on-chip test bus circuit for testing a plurality of circuits and an associated method. The test bus circuit comprises a test bus and a plurality of switching circuits which selectably provide electrical connections between the respective circuits and the test bus. The plurality of switching circuits are configured to transfer an electrical charge between a node disposed within each switching circuit not selected to provide an electrical connection and a respective charge source or sink. The charge source or sink may consist of a low-impedance DC voltage or signal source.
The associated method of the present invention consists of the following steps: (1) providing a test bus; (2) providing a plurality of switching circuits for selectively providing electrical connections between the respective circuits and the test bus; (3) providing one or more charge sources or sinks coupled to the respective switching circuits; (4) setting the respective switching circuit associated with a selected one of the circuits to the conducting state; (5) setting the one or more respective switching circuits associated with the one or more unselected circuits to the non-conducting state; (6) transmitting a test signal between the selected circuit and the test bus via the switching circuit in the conducting state; and (7) transferring an electrical charge between a node disposed within each of the one or more switching circuits in the non-conducting state and the respective charge source or sink.
Some advantages of the test bus circuit and the associated method over earlier testing approaches are as follows. First, the test bus circuit provides a high level of signal integrity and bandwidth for signals to be observed or controlled on an integrated circuit due to its relatively simple and short circuit path. Second, the test bus circuit provides a high level of electrical isolation due to its combined use of multiple, serially-coupled selection devices and the charge-transferring circuit. As a result, signals can be observed and controlled without interfering with the normal operation of nearby or related circuits on the integrated circuit. Third, the test bus circuit minimizes the number of pins necessary for the integrated circuit package to observe or control the signals. Fourth, the test bus circuit is relatively simple to implement and does not significantly increase the size or complexity of the integrated circuit. Fifth, if the test bus circuit includes an optional driven shield, the test bus circuit provides a reduced level of interference with the operation of the circuitry being tested. For these reasons, the test bus circuit is especially suitable for use with high-speed analog or mixed-signal integrated circuits.
These and other features and advantages of the invention will be better appreciated from the following detailed description of the invention together with the appended drawings.